In 28 nanometer (nm) CMOS technologies and above, the orientation of the gates of the transistors on the semiconducting substrate in several directions is possible, in particular in a vertical direction or in a horizontal direction.
On the other hand, in CMOS technologies below 28 nm, the orientation of certain components on the substrate may become critical since such components may, for example, be used only in a single direction. This is the case for example with thin gate oxide MOS transistors typically having an oxide thickness of less than or equal to 2 nm. Typically, such transistors have a vertical gate orientation on the substrate, that is to say perpendicular to an oblique direction of implantation performed in a direction of implantation in such a way as to form doped source and drain zones (commonly designated by the person skilled in the art by the term “Halo” or “pocket”) under the gate of these transistors.
Indeed, lithography and technology constraints may prohibit the use of such transistors in a horizontal direction. Other components remain multi-orientation however. This is the case, for example, with thick gate oxide MOS transistors, typically having a gate oxide thickness of greater than or equal to 3 nm with sufficient gate dimensions measured length-wise along the channel (drain—source distance) of, for example, greater than or equal to 150 nm.
However, in an integrated circuit, certain cells may be disposed according to different orientations as a function of their location on the integrated circuit.
This is the case, for example, with the input/output cells which are generally disposed within a rectangular annulus around the core of the integrated circuit.
Also, typically, as a function of the location of an input/output cell in another branch of the rectangular annulus, certain components, such as, for example thin gate oxide MOS transistors, may then exhibit a vertical orientation or else a horizontal orientation. The transistors exhibiting a horizontal orientation typically must consequently undergo a rotation to again exhibit a vertical gate orientation.
Hence, an approach includes developing, for these advanced technologies, two libraries of cells containing orientation-sensitive components.
Also, the cells of the first library are, for example, intended to be placed in a horizontal branch of the input/output cell annulus so that the thin gate oxide transistors, for example, are vertically oriented.
The homologous cells of the other library are then intended to be disposed in a vertical branch of the annulus so that once again the thin gate oxide transistors exhibit a vertical gate orientation.
That said, not only does such an approach require the development and the qualification of two libraries of cells, but furthermore the designer typically must each time analyze the location of the cell on the integrated circuit so as to extract the corresponding cell from one or the other of the libraries, with the potential risk of errors.